Job description
We are looking for a qualified and highly motivated candidate to lead the RTL Development for GNSS SOC that would power many location services. This would involve in the development of RTL blocks and subsequent implementations. This will be a hands-on position, designing/implementing critical RTL blocks.
Requirements
- MS or PhD degree emphasis in ASIC design
- Five or more years of experience in RTL design using Verilog and System Verilog
- Experience in developing & optimizing RTL blocks and test and verification of DSP blocks
- Previous exposure to physical layer of communication chips such as Wi-Fi, BLE, GNSS, or cellular is a plus
- Design of state machines, data paths, arbitration, and clock domain crossing logic
- Logic synthesis support, FPGA implementation, Timing constraints
- Exposure to Design for Test, understanding of scan concept and writing DFT friendly RTL
- Unified Power Format for simulation, synthesis, and electrical rule checking Equivalence checking
- Accurate power estimation for RTL blocks
- Committed to producing high-quality design
- Team player and excellent interpersonal, communication and writing skills
Job Type: Full-time
Salary: Up to $280,000.00 per year
Benefits:
- Dental insurance
- Flexible schedule
- Paid time off
- Vision insurance
Schedule:
- 8 hour shift
- Monday to Friday
Work Location: Remote
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