Physical Design Hardware Engineering Director
Full Time
San Jose, CA 95134
Posted
Job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Physical Design Hardware Engineering Director will be responsible for leading physical design implementation of family of very large ASICs in latest technology nodes. This individual must be a dynamic “hands-on” leader who will oversee end to end physical design of chip to tapeout, while developing and growing the team. The Director will also identify and lead major initiatives as we continue to scale up and innovate. This person must have a strong technical background in leading large, highly complex chip projects.
The duties and responsibilities of the Director of Hardware Engineering include:
- Lead a talented team of highly accomplished internationally dispersed Place and Route (P&R) physical design engineers
- Hands on top level floorplan, block partitioning and push down, pin placement, high speed clock tree design, place and route, post-route optimization, physical verification, IR drop analysis and sign off, and tapeout for premier HSV products
- With backend driven frontend design implementation in mind, work closely and iterate with architecture, frontend and middle end design teams for optimal design solutions and implementation
- High speed custom clocking and high speed signal intensive routing and mesh design experience
- Work as a team member with peers and across organizational boundaries to build alignment and resolve issues
- Participate in the definition of the technology strategy and roadmap to support the business goals
- Drive strategic technological innovation, develop and grow the team locally and internationally
- Model and reinforce the Cadence Design culture and core values
- Act as an agent of change to instill the culture of high performance, collaboration and innovation.
Qualifications
- Top level chip implementation experience a must
- Experience leading place and route engineering teams to build large, high speed, complex chips on 5nm or below technology nodes
- Experience managing geographically dispersed engineering teams
- Sense of accountability
- Ability to think strategically and also to proactively roll up sleeves and get things done.
- Ability to actively motivate and inspire. A true coach and mentor.
- Demonstrated strong analytical mindset and ability to think outside the box.
- Must be passionate about technology and highly technical
- Bachelors in Computer Science, Electrical Engineering, or related disciplines with at least 10 years of related experience, or Masters with at least 7 years of related experience, or PhD with at least 5 years of related experience
Preferred Technical and Professional Experience
- Hands-on experience in most aspects of chip design: microarchitecture, RTL, verification, physical design, post-silicon validation, etc.
The annual salary range for California is $156,800 to $291,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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