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CAD RTL Synthesis Engineer 172144

THE ROLE:

Do you want to be a key contributor to the Excite team from AMD? We are looking for a Senior CAD Engineer - RTL, Pre-layout Methodology (172144) to be responsible for maintaining and enhancing an established push-button automation flow that performs implementation of RTL through pre-netlist synthesis and static timing analysis. You will also develop parsers to extract and waive key design metrics from industry-standard synthesis and timing reports. These metrics are published to a dashboarding system which the candidate will assist in improving to meet the needs of the RTL design teams.

You will work with a wide array of pre-production frontend design teams to provide solutions to all classes of RTL synthesis problems and support the automation of other flows such as LINT, DFT DRC, CDC, RDC, CLP, and Fishtail as well as a comprehensive regression solution that encompasses all the above.

THE PERSON:

The type of person who will be successful in this role requires a mix of EDA tool competence and TCL-based scripting capability (both in EDA tool environments and stand-alone Linux TCL shell scripts). You should be familiar with in-depth synthesis and timing methodologies, compilation choices, report options, and the full repertoire of frontend (RTL) implementation flows. Prior experience developing complex TCL scripts, including writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters in Synopsys Design Compiler and PrimeTime, is essential.

KEY RESPONSIBILITIES:

• Maintain and enhance a fully automated RTL implementation flow environment facilitating pre-netlist synthesis, static timing analysis, and several other design flows
• Produce scripts to extract metrics from EDA tool shells for reporting purposes
• Provide support for a diverse set of IP designs by assisting designers through design problems and generalizing solutions to roll out to all stakeholders
• Recommend novel visualizations to incorporate into the reporting tools
• Analyze the automation’s architecture and skillfully integrate new features
• Drive closure of support issues

PREFERRED EXPERIENCE:

• Confident experience with RTL Synthesis and Implementation
• Solid digital logic design experience
• Proficient with scripting languages TCL, Perl, Python, CSH
• Proficient with Cron and LSF job control automation
• Self-motivating with a keen eye for maneuvering technical design constraints
• Strong analytical and problem-solving skills
• Good communication skills and experience working on a geographically distributed team

ACADEMIC CREDENTIALS:

• MS (Computer Engineering, Electrical Engineering, or related equivalent)

LOCATION:
San Jose, CA

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Requisition Number: 172144
Country: United States State: California City: San Jose
Job Function: Design

Benefits offered are described here, or click on the link, https://www.amd.com/system/files/documents/us-benefits-at-a-glance-regular-exec-intern-coop.pdf

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.